Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constra

From timing perspective, the designer creates timing constraints for synthesis which are a series of constraints applied to a given set of paths or nets that dictate the desired performance of a design. Constraints may be period, frequency, net skew, maximum delay between end points, or maximum net delay...

Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constra

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This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. 2ff7e9595c